Inter Process Communication: Events

In Verilog, events are static objects that can be triggered via -> operator, and processes can wait for an even to be triggered via the @ operator.

SystemVerilog enhances the Verilog event in several ways.

• The triggered state of Verilog named events has no duration, whereas in SystemVerilog this state persists throughout the time-step in which the event triggered.
• In SystemVerilog an event is a handle to a synchronization object that can be passes around to routines. This feature allows to share events across objects without having to make the events global.

Blocking on the Edge of an Event

Output:
@0: 1: before trigger

@0: 2: before trigger

@0: 1: after trigger

In the above example, one initial block starts, triggers its event, and then blocks on the other event. The second block starts triggers its event(waking up the first), and then blocks on the first event. However, the second thread locks up because it missed the first event, as it is a zero-width pulse.


Instead of using an edge-sesitive block @event_1, use the level sensitive wait(eevent_1.triggerd( )). This does not block if the event has been triggered during this time step. Otherwise, it waits until the event is triggered.

Output:
@0: 1: before trigger
@0: 2: before trigger

@0: 1: after trigger

@0: 2: after trigger

If you use wait(hndshk.triggered( )) in a loop, be sure to advance the time before waiting again. Otherwise, code will go in a zero delay loop as the wait continues over and over again on a single event trigger.

You need to put a delay in the above loop. The edge-sensitive delay statement continues once and only once every event trigger.

Passing Events
An event can be passes as an argument to a routine.

Waiting for multiple events

• Using wait fork

• Counting triggers

• Using thread count